This invention relates to digital graphics display systems, particularly to display refresh memory structures and addressing methods for use in a raster-type graphics display system.
The field of digital computer graphics involves displaying computer-generated images or pictures on a display device such as a cathode ray tube ("CRT"). One way of accomplishing this is to utilize a raster-type display which incorporates as the display device a CRT similar to a television picture tube and generates the image by controlling the intensity of the cathode ray tube's electron beam as it scans the display screen of the CRT in a predetermined pattern of lines or "raster" producing an image formed of a plurality of individual points or "pixels". Raster scan display systems of this type are shown, for example, by Walker, U.S. Pat. No. 4,121,283 and Cheek, et al., U.S. Pat. No. 3,891,982.
As is well understood by those skilled in the art, a raster graphics display system generally comprises, in addition to a raster-type CRT display, a display refresh memory and a graphics computation device. In the bit-per-element type of raster graphics display, which is advantageous because the graphics computation device may operate at a slow rate relative to the display raster, the display refresh memory contains a digital representation of the image to be displayed as individual pixels on the CRT screen, the digital representation of the image to be displayed being a direct mapping from an image stored in the memory to the image which appears on the screen of the CRT. The display refresh memory is continuously read to generate video signals which are applied to the display CRT as it traces out a raster. To provide a continuous and flicker-free display on the CRT this operation, called "display refresh" by those skilled in the art, must be performed at high speed. Raster type displays of this and other types are described in B. W. Jordan and R. C. Barrett, "A Cell Organized Raster Display for Line Drawings," 17 Communications of the ACM 70-77 (Feb. 1974).
The graphics computation device must write the digital representation of the image to be displayed into the display refresh memory, which frequently must be done during the horizontal and vertical scan retrace intervals characteristic of a raster-type display. Since a complex displayed image requires many write operations by the display computation device, the display refresh memory must also be accessed at high speed by the graphics computation device if the display is to be changed or updated rapidly. In many applications, the speed at which the display refresh memory can be read or written therefore places a limit on the speed which the display memory, and thus the displayed image, can be updated.
The "dynamic random-access memory" is a semiconductor memory integrated circuit type which, as is understood by those skilled in the art, is the preferred component from which to construct raster display refresh memories. This is because of its low cost, large number of storage locations or "bits", small size, low power consumption and reasonable read and write access times. However, the speed of dynamic random-access memory is relatively fixed for a given device fabrication technology.
Dynamic random-access memory devices ordinarily require two "row" and "column" addresses, ordinarily in sequence, to select a single storage location therein, the latching of each address taking a certain amount of time. However, memory manufacturers have provided an operation mode for dynamic random-access memory devices called "page mode," which results from the division of the memory locations within a device into large numbers of blocks called "pages", each page corresponding to a single "row" address. Once any memory location within the page has been accessed at normal access speeds, any other memory location on the same page can be accessed at significantly higher speeds than a normal access to an arbitrary memory location by changing only the column address. However, page mode has not heretofore been considered useful in raster display refresh memory systems because of the low probability that memory locations which need to be accessed sequentially by the graphics computation device will fall on the same "page" since the "page" extends in only one dimension of the display memory.
As is shown by Fassbender, U.S. Pat. No. 4,156,905, a method is available for improving access speed in reading a random-access memory comprised of a plurality of random-access integrated circuit memory devices by reading out groups of data into an output register from which the data is more rapidly available. It is nevertheless desirable to utilize the maximum inherent speed of dynamic random-access memory devices, particularly for writing into the refresh memory of a raster graphics display system where rapid changes to the refresh memory can increase the speed at which the displayed image can be updated.
In computer graphics displays, it is often useful to fill a two-dimensional region of the display with a constant value, for example, in clearing the entire display, or a portion thereof, to a background value. This operation involves writing into a large number of display refresh memory storage locations, and thus can be a time-consuming operation which reduces the productivity of the graphics display system. Graphics display refresh memories are generally comprised of a plurality of random-access devices and, as is understood by those skilled in the art, the devices can be read out in parallel and thereafter serialized to obtain sufficient output speed for a video display, the corresponding storage location in each device forming a line of adjacent pixels in a direction parallel to the direction of the display refresh raster scan lines. Simultaneously writing into related storage locations of a plurality of memory devices is also known, as shown by Baltzer, U.S. Pat. Nos. 4,092,728 and 4,150,364. However, the advantage of utilizing this technique in updating a raster graphics refresh memory has apparently not heretofore been recognized, and the speed that can be achieved by reading or writing data to corresponding storage locations in each device simultaneously has heretofore been limited by the inherent random-access speed of the device itself.
Another problem which arises in raster graphics display systems results from certain operations which may be performed by the graphics computation device on data stored in the display memory storage locations. Not only do the same display memory speed limitations which reduce the graphics computation device writing speed also affect its reading speed, but these operations increase the probability of contention for memory access due to the refresh read requirement and the need for the graphics computation device to write into the memory. It is therefore desirable to provide a rapid means of accessing data in the display memory for manipulation by the graphics computation device while reducing the probability of memory contention.
By way of background, other technical references of general interest are: Lee et al., U.S. Pat. No. 3,411,142; Parsons et at., U.S. Pat. 4,099,259; Sugarman, U.S. Pat. No. 3,581,290; and Naka, U.S. Pat. No. 3,735,383; Bringol, U.S. Pat. No. 4,240,075; Hogan et al., U.S. Pat. No. 3,641,559; Watson et al., U.S. Pat. No. 3,787,673; and Suenaga, Kamae and Kobayashi, "A High-Speed Algorithm for the Generation of Straight Lines and Circular Arcs," 28 IEEE Transactions on Computers 728-36 (Oct. 1979).